Build it up. Nat. Electron. 7, 415 (2024).
Narayanan, V. Going vertical: the future of electronics. IEEE Micro 39, 6–7 (2019).
Datta, S. et al. Back-end-of-line compatible transistors for monolithic 3-D integration. IEEE Micro 39, 8–15 (2019).
Bishop, M. D., Wong, H. -S. P., Mitra, S. & Shulaker, M. M. Monolithic 3-D integration. IEEE Micro 39, 16–27 (2019).
Jayachandran, D., Sakib, N. U. & Das, S. 3D integration of 2D electronics. Nat. Rev. Electr. Eng. 1, 300–316 (2024).
Vianello, E. & Payvand, M. Scaling neuromorphic systems with 3D technologies. Nat. Electron. 7, 419–421 (2024).
Sheikh, F., Nagisetty, R., Karnik, T. & Kehlet, D. 2.5D and 3D heterogeneous integration: emerging applications. IEEE Solid-State Circuits Mag. 13, 77–87 (2021).
Bourjot, E. et al. Towards 5 μm interconnection pitch with die-to-wafer direct hybrid bonding. In Proc. 71st Electronic Components and Technology Conference (ECTC), 470–475 (IEEE, 2021).
Dhananjay, K., Shukla, P., Pavlidis, V. F., Coskun, A. & Salman, E. Monolithic 3D integrated circuits: recent trends and future prospects. IEEE Trans. Circuits Syst. II Express Briefs 68, 837–843 (2021).
Chang, S. W. et al. First demonstration of CMOS inverter and 6T-SRAM based on GAA CFETs structure for 3D-IC applications. In Proc. International Electron Devices Meeting (IEDM) 11.17.11–11.17.14 (IEEE, 2019).
Shih, B. J. et al. 3DIC with stacked FinFET, inter-level metal, and field-size 25×33 mm2 single-crystalline Si on SiO2 by elevated-epi. In Proc. Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) 1–2 (IEEE, 2024).
Shih, B.-J. et al. Elevated-epi (Elepi) technique for 3D IC with stacked FinFETs, interlevel metal, and 25 × 33 mm2 single-crystalline silicon on SiO2. IEEE Trans. Electron Devices 71, 7978–7983 (2024).
Oota, M. et al. 3D-stacked CAAC-In-Ga-Zn oxide FETs with gate length of 72 nm. In Proc. International Electron Devices Meeting (IEDM) 3.2.1–3.2.4 (IEEE, 2019).
Chang, S. W. et al. First demonstration of heterogeneous IGZO/Si CFET monolithic 3D integration with dual workfunction gate for ultra low-power SRAM and RF applications. In Proc. International Electron Devices Meeting (IEDM) 34.34.31–34.34.34 (IEEE, 2021).
Yuvaraja, S. et al. Three-dimensional integrated metal-oxide transistors. Nat. Electron. 7, 768–776 (2024).
Yuvaraja, S. et al. Three-dimensional integrated hybrid complementary circuits for large-area electronics. Nat. Electron. 8, 969–980 (2025).
Son, Y., Frost, B., Zhao, Y. & Peterson, R. L. Monolithic integration of high-voltage thin-film electronics on low-voltage integrated circuits using a solution process. Nat. Electron. 2, 540–548 (2019).
Shulaker, M. M. et al. Three-dimensional integration of nanotechnologies for computing and data storage on a single chip. Nature 547, 74–78 (2017).
Srimani, T. et al. Heterogeneous integration of BEOL logic and memory in a commercial foundry: multi-tier complementary carbon nanotube logic and resistive RAM at a 130 nm node. In Proc. Symposium on VLSI Technology 1–2 (IEEE, 2020).
Srimani, T. et al. Foundry monolithic 3D BEOL transistor + memory stack: iso-performance and iso-footprint BEOL carbon nanotube FET+RRAM vs. FEOL silicon FET+RRAM. In Proc. Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) 1–2 (IEEE, 2023).
Zhang, Y. et al. 3D stackable CNTFET/RRAM 1T1R array with CNT CMOS peripheral circuits as BEOL buffer macro for monolithic 3D integration with analog RRAM-based computing-in-memory. In Proc. International Electron Devices Meeting (IEDM) 1–4 (IEEE, 2023).
Zhu, J. et al. Low-thermal-budget synthesis of monolayer molybdenum disulfide for silicon back-end-of-line integration on a 200 mm platform. Nat. Nanotechnol. 18, 456–463 (2023).
Kang, J.-H. et al. Monolithic 3D integration of 2D materials-based electronics towards ultimate edge computing solutions. Nat. Mater. 22, 1470–1477 (2023).
Jayachandran, D. et al. Three-dimensional integration of two-dimensional field-effect transistors. Nature 625, 276–281 (2024).
Lu, D. et al. Monolithic three-dimensional tier-by-tier integration via van der Waals lamination. Nature 630, 340–345 (2024).
Pendurthi, R. et al. Monolithic three-dimensional integration of complementary two-dimensional field-effect transistors. Nat. Nanotechnol. 19, 970–977 (2024).
Kim, K. S. et al. Growth-based monolithic 3D integration of single-crystal 2D semiconductors. Nature 636, 615–621 (2024).
Guo, Y. et al. Van der Waals polarity-engineered 3D integration of 2D complementary logic. Nature 630, 346–352 (2024).
Colinge, J.-P. et al. Nanowire transistors without junctions. Nat. Nanotechnol. 5, 225–229 (2010).
Vandooren, A. et al. Demonstration of 3D sequential FD-SOI on CMOS FinFET stacking featuring low temperature Si layer transfer and top tier device fabrication with tier interconnections. In Proc. Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) 330–331 (IEEE, 2022).
Radu, I. et al. Ultimate layer stacking technology for high density sequential 3D integration. In Proc. International Electron Devices Meeting (IEDM) 1–4 (IEEE, 2023).
Inoue, F. et al. Characterization of extreme Si thinning process for wafer-to-wafer stacking. In Proc. 66th Electronic Components and Technology Conference (ECTC) 2095–2102 (IEEE, 2016).
Irfan, H. M., Lee, C.-Y., Mazumdar, D., Aryanfar, Y. & Wu, W. Improvement of material removal rate and within wafer non-uniformity in chemical mechanical polishing using computational fluid dynamic modeling. J. Manuf. Mater. Process. 9, 95 (2025).
Feng, W. et al. Wafer-to-wafer bonding fabrication process-induced wafer warpage. IEEE Trans. Semicond. Manuf. 36, 398–403 (2023).
Seok, S., Park, H. & Kim, J. Characterization and analysis of metal adhesion to parylene polymer substrate using scotch tape test for peripheral neural probe. Micromachines 11, 605 (2020).
Moriceau, H. et al. Overview of recent direct wafer bonding advances and applications. Adv. Nat. Sci.: Nanosci. Nanotechnol. 1, 043004 (2010).
Kim, S.-G., Kim, G.-S., Kim, S.-H. & Yu, H.-Y. Low-temperature hybrid dopant activation technique using pulsed green laser for heavily-doped n-type SiGe source/drain. IEEE Electron Device Lett. 39, 1828–1831 (2018).
Sklenard, B. et al. Low temperature junction formation by solid phase epitaxy on thin film devices: atomistic modeling and experimental achievements. In Proc. International Workshop on Junction Technology (IWJT) 1–6 (IEEE, 2014).
Gundapaneni, S., Ganguly, S. & Kottantharayil, A. Bulk planar junctionless transistor (BPJLT): an attractive device alternative for scaling. IEEE Electron Device Lett. 32, 261–263 (2011).
Doris, B. et al. Device design considerations for ultra-thin SOI MOSFETs. In Proc. International Electron Devices Meeting 27.3.1–27.3.4 (IEEE, 2003).
Scognamiglio, L., Mo, F., Spano, C. E., Vacca, M. & Piccinini, G. Simulation study on the impact of miniaturization in 3 nm node 3D junctionless transistors. IEEE Trans. Nanotechnol. 24, 102–109 (2025).
Arora, N. D., Hauser, J. R. & Roulston, D. J. Electron and hole mobilities in silicon as a function of concentration and temperature. IEEE Trans. Electron Devices 29, 292–295 (1982).
Esseni, D. et al. Low field mobility of ultra-thin SOI N- and P-MOSFETs: Measurements and implications on the performance of ultra-short MOSFETs. In Proc. International Electron Devices Meeting (IEDM) 671–674 (IEEE, 2000).
Vandooren, A. et al. 3D sequential stacked planar devices on 300 mm wafers featuring replacement metal gate junction-less top devices processed at 525 °C with improved reliability. In Proc. IEEE Symposium on VLSI Technology 69–70 (IEEE, 2018).
Franklin, A. D. Nanomaterials in transistors: from high-performance to thin-film applications. Science 349, aab2750 (2015).
Yang, S. et al. A high performance 180 nm generation logic technology. In Proc. International Electron Devices Meeting (IEDM) 197–200 (IEEE, 1998).
Ando, T. Ultimate scaling of high-κ gate dielectrics: higher-κ or interfacial layer scavenging? Materials 5, 478–500 (2012).
Jacoboni, C., Canali, C., Ottaviani, G. & Alberigi Quaranta, A. A review of some charge transport properties of silicon. Solid-State Electron. 20, 77–89 (1977).
Zhu, W. J. & Ma, T. P. Temperature dependence of channel mobility in HfO2-gated NMOSFETs. IEEE Electron Device Lett. 25, 89–91 (2004).
Ku, B. W., Song, T., Nieuwoudt, A. & Lim, S. K. Transistor-level monolithic 3D standard cell layout optimization for full-chip static power integrity. In Proc. IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) 1–6 (IEEE/ACM, 2017).
Jang, H. et al. Quantum confinement effects in transferrable silicon nanomembranes and their applications on unusual substrates. Nano Lett. 13, 5600–5607 (2013).
Rogers, J. A., Lagally, M. G. & Nuzzo, R. G. Synthesis, assembly and applications of semiconductor nanomembranes. Nature 477, 45–53 (2011).
Zhang, Y. et al. A smart coating with integrated physical antimicrobial and strain-mapping functionalities for orthopedic implants. Sci. Adv. 9, eadg7397 (2023).
Mack, S., Meitl, M. A., Baca, A. J., Zhu, Z.-T. & Rogers, J. A. Mechanically flexible thin-film transistors that use ultrathin ribbons of silicon derived from bulk wafers. Appl. Phys. Lett. 88, 213101 (2006).
Cohen, S. S. & Gildenblat, G. Sh. in Metal–Semiconductor Contacts and Devices. VLSI Electronics Microstructure Science series, Vol. 13 (ed. Einspruch, N. G.) 213–310 (Academic Press, 2014).
Chizh, K. V. et al. Low-temperature formation of platinum silicides on polycrystalline silicon. J. Alloys Compd. 843, 155908 (2020).
Takeuchi, H., Wung, A., Xin, S., Howe, R. T. & King, T.-J. Thermal budget limits of quarter-micrometer foundry CMOS for post-processing MEMS devices. IEEE Trans. Electron Devices 52, 2081–2086 (2005).
Cavalcante, C. et al. 28 nm FDSOI CMOS technology (FEOL and BEOL) thermal stability for 3D sequential integration: yield and reliability analysis. In Proc. IEEE Symposium on VLSI Technology 1–2 (IEEE, 2020).
Kanarik, K. J., Tan, S. & Gottscho, R. A. Atomic layer etching: rethinking the art of etch. J. Phys. Chem. Lett. 9, 4814–4821 (2018).
Shamiryan, D., Abell, T., Iacopi, F. & Maex, K. Low-k dielectric materials. Mater. Today 7, 34–39 (2004).
De Wolf, I. Micro-Raman spectroscopy to study local mechanical stress in silicon integrated circuits. Semicond. Sci. Technol. 11, 139 (1996).
Bishop, M. D. et al. Fabrication of carbon nanotube field-effect transistors in commercial silicon manufacturing facilities. Nat. Electron. 3, 492–501 (2020).
