Synaptic and neural behaviours in a standard silicon transistor

Devices under test

The devices were standard polysilicon/SiON gate-stack bulk-silicon MOSFETs with an n-channel length of 180 nm (thin oxide, approximately 3.5 nm) or 500 nm (thick oxide, approximately 10 nm) from a standard, commercial CMOS technology. All devices had an n–p junction connected to the gate to avoid damage due to the antenna effect during device fabrication, a typical design requirement when large probing pads are directly connected to a thin oxide.

Basic device characterization

For the current versus voltage (I–V) curves, we characterized the current flowing through the drain and the source terminals (I_D) when the voltage between them (V_D) was ramped and the gate electrode was subjected to a constant voltage (V_G) while keeping the bulk terminal grounded (as in most applications) or floating. The electrical characterization was performed with a probe station (EPS150, FormFactor) connected to a semiconductor parameter analyser (Keysight B1500A). All the I–V curves under d.c. voltages (Fig. 2 and Supplementary Figs. 2–7) were collected using ramped voltage sweeps at limited auto ranging. For constant sweep rate measurements at rates below 100 V s⁻¹ (Supplementary Figs. 8, 19 and 14), limited auto ranging was configured starting at a range of 100 nA to ensure a constant delay time between measurements (verified by storing timestamps for every measurement), and the step size was increased (for high sweep rates) or the delay time was extended (for very low sweep rates) to increase the sweep rate parametrically. In all cases, three source measurement units (SMUs) were used for the drain, source and gate of the floating-bulk device and another SMU was used to bias the gate of the substrate current control transistor (V_G2). The source for this transistor was grounded through the ground unit of the semiconductor parameter analyser. The drain was connected to the bulk tap connection of the floating-bulk device. Retention and pulsed-read retention measurements (Supplementary Figs. 25, 26 and 28) were carried out in Keysight’s EasyEXPERT environment using a custom arrangement of I–V, I–V pulse and I–V list sweeps. In the floating-bulk and non-floating-bulk retention tests (Supplementary Fig. 26), which addressed the permanent nature of the device state, the substrate tap contact was opened using the built-in SMU switch for the floating-bulk writing procedures and then grounded through the SMU during the retention period.

Physical simulations

Physical simulations of the floating-bulk transistors were carried out with commercial TCAD software (Sentaurus TCAD, Synopsys). The two-dimensional device structure was built using a structure descriptive approach and based on commonly known parameters of the technology node at which the devices under test were fabricated. Next, the device structure was optimized by simulating the nominal (grounded bulk) quasi-stationary I_D–V_G characteristics and calibrated against experimental data. Once good agreement was reached, transient I_D–V_G simulations including impact-ionization physics were run to calibrate the impact-ionization model parameters to the nominal substrate currents in the device. With this calibration fixed, we ran transient simulations of I_D–V_D at different V_D sweep rates within a mixed-mode environment that connected the bulk biasing network to the substrate contact of the two-dimensional device structure. The bulk biasing network had a constant value resistance (R_sub) or an n-channel transistor modelled in SPICE BSIM and biased by an independent gate voltage source. In all cases, a bulk connected capacitance (C_bulk) was included to account for experimental and device connection parasitics. The complete Sentaurus Workbench project, including the command and parameter files, is available through a public repository at https://doi.org/10.5281/zenodo.13843362 (ref. ⁴⁹). For more details of the models used and the project structure, see Supplementary Note 8.

Punch-through impact ionization

In the devices under test (Fig. 2), when V_G > 0.5 V, avalanching was observed as a slight current increase, like that observed in partially depleted silicon-on-insulator MOSFETs⁵⁰. This effect is often referred to as the kink effect²⁷. By contrast, when V_G was between 0.3 and 0.5 V, this phenomenon was manifest as a gate-voltage-dependent hysteresis⁵¹ as wide as 0.5 V, which could be precisely controlled through V_G (Supplementary Fig. 2). Measurements of the grounded-bulk terminal current show that the impact-ionization hole currents were as large as about 10 μA under nominal voltages for 180- and 500-nm devices (Supplementary Figs. 4 and 10, respectively). In the floating-bulk configuration, although electrons were collected by the drain, the excess holes tended to forward bias the source junction (Supplementary Note 3) and introduce a positive feedback during the impact-ionization process, driving the device into an avalanche regime in which the current (I_D > 1 μA) was limited only by the spreading resistance of the bulk, with a slight dependence on V_G (through modulation of the depletion region). This universal phenomenon is ascribed to the structure of the MOSFET device, as the same behaviour was observed in floating-bulk thick-oxide MOSFETs (500 nm channel length and approximately 10 nm oxide thickness). In these devices, the hysteresis reached widths of 0.8 V at V_G = 0 V and was highly reproducible over several devices with a very low variability (Supplementary Fig. 3) and a wide dynamic range of over 4 orders of magnitude in current, comparable to other threshold devices proposed in the literature as neurons^29,52,53. Like the results in Fig. 2g for 180-nm devices, this was also a highly repeatable regime for 500-nm transistors, as shown for the more than 70,000 cycles under fast ramped tests at rates of 5,500 V s⁻¹, which measured the device current with high temporal resolution (1 µs) at a peak V_D = 4.25 V. The result shows a resistance window over ×10 (limited only by the dynamic range of the measurement unit at a fixed amplifier gain) with very low cycle-to-cycle variability (Supplementary Fig. 8).

Bulk bias control transistor (two-transistor cell)

The effective resistance of a bulk connection to any CMOS device is always determined by device design and processing (such as doping profiles, die size, back-wafer contact surface and top-wafer bulk contact design). Therefore, die-to-die variations can occur during characterization after dicing. Identical 180-nm transistors from different dice can show different hysteretic characteristics depending on variations of the effective resistance of the back-wafer connection. For 30 dice extracted from a multi-project wafer, this was found to depend on wafer position (Supplementary Fig. 5). A bulk control transistor can effectively mask these variations and fix the operating conditions of the floating-bulk device (see detailed characterization of the effective R_B resistance as a function of V_G2 in Supplementary Fig. 6). This ensures the desired neural behaviour, despite die-to-die (or even wafer-to-wafer) variability, as can be seen from the I_D–V_D curves carried out on the same 30 dice but with the control device biased at V_G2 = 1.3 V in all cases (Supplementary Fig. 7).

Time-domain measurements

All the time-resolved I–V curves under pulse or fast ramp modes (sweep rates over 10 V s⁻¹) were collected using a two-channel waveform generator and fast measurement unit (Keysight B1530 WGFMU) connected to the drain and source. Two SMUs established a constant bias gate voltage to the device under test (V_G) and to the substrate current controlling device (V_G2) throughout the whole process. These measurements (Figs. 3, 4 and 5d and Supplementary Figs. 15–24) were carried out in a custom environment programmed in MATLAB and C++ running on a personal computer with a GPIB/USB connection to the B1500 mainframe. The environment allowed to rapidly optimize the pulse and ramp parameters (amplitude and timing). We could perform several iterations of long acquisitions, which maximized the use of the instrument memory, for endurance and cycling tests lasting several hours without user interaction.

Neuro-synaptic tuning experiments

To extract the firing time and energy, we applied V_G2 = 1.6 V and, by controlling the transistor gate voltage (V_G) between 0.35 and 0.45 V (Supplementary Fig. 19a–c), we tuned the neuron firing times between 10 µs and 2 ms for V_spike between 3.5 V and 4.5 V (Fig. 3c, left axis). Changing the bulk biasing conditions through V_G2 had a trivial effect on the firing time within this regime, as shown by the negligible difference between measurements performed at V_G2 = 1 or 1.6 V (Supplementary Fig. 19d). This behaviour was also controlled using oxide transistors that were 500 nm in length and thickness (Supplementary Fig. 20), for which equivalent dynamics was observed but at lower currents (down to 10 nA) and slightly higher voltages (up to 5 V). This is of interest for the device-level optimization of the neural behaviour through design variables, such as transistor size, oxide or threshold voltage, which is typically offered in standard CMOS processes.

To characterize the leaky feature (Fig. 3b and Supplementary Fig. 21), we applied a single voltage pulse of 4.5 V for 1 ms to fire the neuron. The relaxation transient was extracted at a constant read voltage of 1 V. This time, by using different V_G2 values (from 0 to 1.8 V) at constant V_G, we showed that the relaxation transient can be tuned from approximately 50 μs to tens of milliseconds. A long-term change of the resistance from a HRS to a LRS was visible (Supplementary Fig. 21d). The characteristic relaxation time (τ_r) was extracted through an exponential decay fit, and the synaptic update ratio was evaluated after a 30-ms window (R_HRS/L_LRS, as depicted in Supplementary Fig. 21d).

To mimic biological processes, neuron devices need to show a characteristic responsiveness to frequencies that are typically in the range 20 Hz to 20 kHz (for example, for frequency mapping of audio signals). To assess this, we used a train of spikes of fixed duration (t_spike = 5 µs) and different amplitudes (V_spike between 3.6 and 4.5 V) and frequencies (between 20 Hz and 200 kHz) at a fixed V_G = 0.4 V and V_G2 = 0.8 or 1.3 V, thus covering different relaxation dynamics. Under these conditions, we extracted the time elapsed until the neuron fired at each given input (Supplementary Fig. 22) and parametrically mapped it in Fig. 3d. The response can be tailored according to the system needs and to the process being mimicked. For tonotopic mapping²⁹, different devices can be biased to provide a specific firing time at different frequencies to provide a full range of audio signal responses that spans from the lowest audible frequencies to signals well into the ultrasound range, such as for the efficient implementation of a smart hearing system. The wide configurability of the neuron can find application in various general-purpose neuromorphic implementations.

Charge-trapping mechanisms in long-term synaptic behaviour

For a detailed discussion, refer to Supplementary Note 4 and figures therein. From the theoretical aspect, it is probable that the injection of hot electrons during the reset (negative drain bias) in the floating-bulk condition contributes to the increase of the threshold voltage. Moreover, de-trapping some of this injected charge or hot-hole injection may be the mechanism through which the threshold voltage is reduced back to its initial value. In the reset process (the increase of the threshold voltage or, in other words, the increase of the resistance under a constant bias), a negative bias is applied to the drain in the floating-bulk condition. Note that if the transistor bulk was indeed grounded, the current would be determined by the forward bias drain–bulk junction and would rise rapidly, as it would be limited only by the semiconductor spreading resistance and the interconnect resistance (see measurements and TCAD simulation results for these conditions in Supplementary Fig. 27a). However, with the floating bulk, the decreasing drain voltage tends to forward bias the drain–bulk junction, lowering the electrostatic potential of the silicon bulk and inducing an inversion channel under the gate (recall that V_G was held at constant voltage). As the source was held at 0 V, it was biased above the electrostatic potential of the bulk and large currents were driven in the device channel. When the drain voltage was sufficiently negative, there were energetic electrons in the vicinity of the source terminal (see impact-ionization rates from the TCAD calculations in Supplementary Fig. 27b), and these were probably injected into the gate oxide. This would, logically, result in an increase of V_th and therefore a reduction in the current drive capability. This would tend to shift V_th to a higher voltage, therefore lowering the drive current capability of the transistor, which translates to a high resistivity state under read conditions.

During the set process, some de-trapping of the charge generated during the reset sweep would be expected, but the effect of hot electrons is typically non-reversible⁵⁴ (at least without annealing conditions). Therefore, it is probable that the injection of holes through the gate dielectric on the drain side may also take place under impact-ionization conditions. This well-known process has been observed in standard silicon transistors since 1981^55,56,57. This phenomenon takes place at high drain voltages, where band-to-band tunnelling is likely in the drain–bulk junction and highly energetic holes and electrons are present under impact-ionization conditions. As excess holes are not collected by the bulk current in the floating-bulk condition and the density of holes tends to increase at the oxide interface close to the drain (as discussed previously in Supplementary Fig. 12 and Supplementary Note 3), the conditions are suitable for hole injection. As with electrons, hot holes can be injected through the gate dielectric if they have enough energy to overcome the energy barrier. As a result, this effect has been observed to be responsible for the read disturb instability in EEPROM^58,59 and is employed as an erase mechanism in some commercial embedded Flash memories³⁹, as injected trapped holes result in a decrease of the threshold voltage. In such cases, the hot holes that are injected can be effectively concealed within the floating-gate structure, but in standard MOSFET structures, fewer holes can become trapped in defect centres of the gate oxide or spacer oxide of the MOSFET structure.

Short-term plasticity experiments

In Fig. 4a, we applied pulse trains with a constant amplitude in groups of 15 potentiation pulses (V_pot = 4.1 V and t_pot = 5 μs) followed by 20 depression pulses (V_dep = −0.25 V and t_dep = 1 μs). This set of potentiation and depression pulses was intercalated by a read pulse (V_read = 0.3 V and t_read = 5 μs) that measured the resistance of the device. For Fig. 4b, we tuned the amplitudes (V_pot = 4.0 V, V_dep = −0.4 V and V_read = 0.3 V) and applied this protocol continuously for approximately 200,000 cycles (approximately 7 million pulses; Supplementary Fig. 23). We extracted statistics for the obtained synaptic weight after each pulse (Supplementary Fig. 23a). In Fig. 4d, the potentiation process consisted of 21 potentiation pulses at a lower potentiation voltage (V_pot = 2.8 V and V_read = 0.75 V) followed by a single depression pulse (V_dep = −0.7 V; Supplementary Fig. 24). This process allowed us to rapidly reset the neuro-synaptic characteristic of the device to a quiescent initial state. We observed that the depression pulse effectively reset the synapse to its initial weight, which was tunable over a window of approximately ×10, following a roughly bilinear characteristic (Fig. 4d). The observed cycle-to-cycle variability was ascribed to drift in the time-domain measurement and some degree of probe-to-pad contact stability in pulsed experiments spanning several hours (760,000 cycles or 16.7 million pulses; Supplementary Fig. 24). In Fig. 4e, the potentiation sequence (learning) was the same as for Fig. 4d, whereas the synaptic decay through time (forgetting) was performed under a slightly lower constant read voltage (V_read = 0.7 V).

Neuron bursting, spike frequency adaptation measurements

Bursting-mode neuron measurements (Supplementary Figs. 29–31) were carried in the same probe station set-up by forcing a current through the SMU connected to the drain of the floating-bulk device. This terminal was split and fed to the input of a high-input-impedance low-noise voltage follower (TLC2262). Its output drove a channel of a digital sampling oscilloscope (MSO-X 3024G, Keysight). The oscilloscope–semiconductor parameter analyser tandem was synchronized using a MATLAB script and the whole parametric space of V_G1, V_G2 and I_excitatory was swept. The action potential bursts were captured in each condition (Supplementary Fig. 31a). Further details and results are given in Supplementary Note 6.