Directly probing the carrier transfer length in 2D-material transistors

In response to the increasing needs of artificial intelligence computations and rising requirements in data centres and mobile devices, the necessity to fabricate transistors that are high-density, high-performance and energy-efficient has become increasingly urgent. For decades, the scaling of silicon has adhered to Moore’s law, yet it now approaches a challenging phase as it nears the physical limits of Si. Among the option for post-Si channel materials, two-dimensional (2D) materials emerge as the cornerstone for the continuing scaling of transistors², offering potential advantages in low-power consumption. This miniaturization primarily depends on the scaling of channels and contacts, which involves not only shortening the channel length but also scaling down the size of metal contacts, the crucial gateways for current injection. This presents a marked challenge because shrinking their size can often lead to performance-limiting contact resistance. Substantial efforts have been made in understanding the scaling limitation for ultrathin 2D materials, in particular, on the channel scaling of monolayer (ML) 2D materials for the transistors beyond 1 nm technology node^3,4. However, the equally important metal contact scaling has received very little attention, and it presents a tough challenge, especially for 2D material-based field-effect transistors (FETs), because their current crowding is expected to be prominent at the nanoscale contacts. Numerous research groups have ventured into modifying contact materials or adopting interface engineering techniques to mitigate the high contact resistance issue^{6,7,8,9,10,11,12}. However, the task of contact size reduction is still mostly unexplored. One of the inherent challenges lies in the determination of transfer length (L_T), which is the effective current injection region between metal contact and 2D material, and it corresponds to the limitation of contact size scaling. A previous study¹³ used ab initio simulation to demonstrate that the electron injection from a top metallic contact into underlying 2D material can occur either at the edge or the overlap area of metal/2D materials interface, depending on the interface properties, implying that the carrier transport strongly relies on contact metals, 2D channel materials and thicknesses, and metal/2D interface quality. Furthermore, precise and controllable fabrication of sub-20-nm contacts is still very challenging, which makes it more difficult to determine the contact size limit experimentally.

Early studies have made notable strides in this area. A previous study¹⁴ used an ultrahigh-vacuum metal deposition method to fabricate few-layer MoS₂ transistors with an Au contact, estimating a transfer length of around 35 nm. Another study¹⁵ demonstrated that Ni contacts on few-layer MoS₂ transistors, fabricated using e-beam lithography, maintained on-state current even with a contact length of 13 nm, suggesting an L_T ≤ 13 nm for Ni and few-layer MoS₂. MoS₂ FETs with Au/Ni contact lengths varying from 300 nm to 20 nm on ML 2D FETs were fabricated in ref. ⁸, indicating a transfer length of approximately 45 nm. Recently, another study¹⁶ has shown that semimetal antimony (Sb) as a contact metal in ML-MoS₂ transistors can maintain on-state current even with a 30 nm contact length. Extrapolating through TCAD (technology computer-aided design) model simulation, the study predicted a contact length scaling for Sb-MoS₂ at approximately 15 nm. Various reported values of L_T estimation for MoS₂ are summarized in Extended Data Table 1. Despite these advancements, all the transfer length estimation still relies on theoretical simulation or extrapolation of a series of devices with varied metal sizes through theoretical models^7,17,18,19, where many assumptions are unavoidable to approximate the transfer length. Until now, there is still a lack of direct measurement for the nano-scaled transfer length at the 2D/metal interfaces in a transistor device, that is urgently needed to understand the scaling constraints for advanced electronics.

Here, we use cross-sectional scanning tunnelling microscopy and spectroscopy (XSTM/S), with the ability to probe electronic structures on a sub-nanometre scale while applying an in situ operating voltage between source and drain, to measure the current injection length in metal–2D contact. As a semimetal such as bismuth (Bi) or Sb has been demonstrated as almost barrier-free and exhibits extremely low contact resistance on MoS₂, with great potential to reach the ultra-scaled contact size^6,9,11, Bi-contacted ML-MoS₂ is selected in the study to understand the limit of contact scaling. Note that compared with 2D few layers, the ML is considered more suitable for advanced scaling owing to its ultimately thin thickness for desired gate controllability. With this, we have made the direct nanometre-scale experimental measurements of the current injection length of 2D ML transistors. Our findings show a current injection length of approximately 2.0–3.0 nm for Bi on ML-MoS₂ transistor at room temperature, meeting the metal width requirement in the 1 nm technology node¹ (<18 nm). We anticipate that this proposed metrology will serve as a stepping stone for further experimental endeavours in contact engineering, nanoscale device physics and advanced electronics.

To validate the good electrical contact between chemical vapour deposition (CVD)-grown MoS₂ (see the Methods for the growth) and Bi, back-gated MoS₂ FETs with varying channel lengths were fabricated, and the transfer length method (TLM) was used for characterizing contact resistance. The optical image and schematic of the measured MoS₂ device are shown in Fig. 1a. The flowchart of MoS₂ device fabrication with SiO₂ (100 nm) as the gate dielectric is shown in Extended Data Fig. 1 and can be referred to in previous publications^20,21. Figure 1b shows the output characteristics, source–drain current (I_DS) and source–drain voltage (V_DS) as a function of gate voltage (V_GS) in one of the measured MoS₂ FETs, where the measured I_DS exhibits a linear dependence on the V_SD. The α value, derived using the power law I_DS = V_DS^α, is estimated to be approximately 1.00, as shown in Fig. 1b (inset), confirming an ohmic-like contact behaviour⁵. Figure 1c shows the transfer curves (I_DS–V_GS) as a function of V_DS in the identical device, exhibiting moderate on-current density and standard n-channel conducting behaviour with an on/off current ratio of larger than 10⁶ at V_DS = 1 V and within the V_GS range of ±40 V, as shown in Fig. 1c (inset). To estimate the contact resistance (R_c) in our MoS₂ FETs, R_c is extracted from the relationship between total resistance (2R_c) and channel lengths at a consistent gate voltage, as shown in Fig. 1d. The value of R_c is determined by half of the y-axis intercept resulting from a linear fit to the data points. Consequently, the R_c for a Bi contact to ML-MoS₂ is as low as about 70 Ω μm at a carrier concentration of 6.8 × 10¹²cm⁻². The carrier concentration induced by electrostatic gating is estimated by assuming a simple linear charge dependence on the gate voltage. The corresponding I_DS–V_DS curves for the determination of contact resistance are provided in Extended Data Fig. 2. Figure 1d (inset) shows not only the total contact resistance but also transfer length (2L_T), determined using the extrapolation method from the TLM. The minimum L_T obtained is approximately 9.25 nm. The gate dependence of R_c and L_T extracted from the TLM is summarized in Supplementary Table 1, which shows that L_T increases with increasing gate voltage (that is, higher carrier concentration). The L_T values from the TLM will be compared with those derived from the XSTM measurement later.

a, Optical image (top) and schematic (bottom) of one selected MoS₂ device for the TLM. b, Typical I_DS–V_DS curves as a function of V_GS. The inset is the double-logarithmic I_DS−V_DS plot, in which the power law of α is about 1.00, indicating an ohmic-like behaviour in the Bi-contacted MoS₂ FETs. c, Typical I_DS–V_GS curves as a function of V_DS. The inset is the logarithmic I_DS–V_GS plot, in which the on/off ratio is larger than six orders of magnitude. d, Correlation between the measured total resistance and the channel length measured for the TLM devices on SiO₂(100 nm)/Si substrate. The inset shows a contact resistance (R_c) of about 70 Ω μm and the transfer length (L_T) by the extrapolation method. Scale bar, 2 μm (a).

In this work, a Bi-contacted ML-MoS₂ transistor with a channel length of 2 μm is prepared for XSTM measurements. We design a device based on the CVD MoS₂ ML contacted with two-terminal Bi source and drain metals, in which the main part of the device fabrication is shown in Fig. 2a. To directly probe the length of carrier injection at the contact edge of Bi-contacted MoS₂ transistors, we develop device-operating XSTM in this work, in which the ML-MoS₂ transistor with Bi contacts is cleaved with mechanical force in an ultrahigh-vacuum chamber (Fig. 2b). This methodology avoids environmental contamination and molecular absorption that may affect the characterization of their electronic structures (for details, see Supplementary Note 1). Meanwhile, it also provides the ability to directly measure the electronic structure at heterointerfaces. Furthermore, to investigate the carrier transport behaviour under operating conditions, we successively applied the V_DS on the cleaved transistor in an ultrahigh-vacuum chamber (Fig. 2c) to generate a current from the drain to the source contact, while applying the V_G between the source and the gate (Si substrate). For device performance of the transistor for XSTM measurement, refer to Supplementary Note 2. We conduct the operando XSTM spectroscopy measurement at the ML-MoS₂ at underlying the Bi drain contact and at the channel region to investigate the spatially resolved local electronic structure of MoS₂ with and without applying V_DS. Figure 2d schematically shows the cross-sectional structure of the Bi drain contact with MoS₂, in which we define the physical edge of Bi metal towards the channel side as the contact edge (C.E.). Figure 2e,f shows the cross-sectional STM topography of the Bi-contacted MoS₂ transistor around the C.E. Furthermore, the position of the ML-MoS₂ film was delineated using the density-of-states mapping in XSTM spectroscopic measurements (Fig. 2g). This identification is also consistent with separate cross-sectional scanning transmission electron microscopy (STEM) and energy-dispersive X-ray spectroscopy measurements (Fig. 2h).

a, Schematic of the sample structure. b, Cross-sectional STM sample cleaved in ultrahigh vacuum. The channel length and the contact length of the sample device are 2 µm. c, XSTM probing on the cross-sectional side of the sample, in which a source–drain bias V_DS is applied during the STM measurement, with V_S denoting the sample bias for the STM process. d, Schematic of the device structure close to the Bi drain contact and MoS₂. The edge of the Bi drain contact is labelled as C.E. (contact edge). e, Large-area topography image showing the overall cleaved surface at the C.E. region, from the Bi contact, across the HfO₂ dielectric, to the Si substrate. f, High-resolution topography image focused on the C.E. region with first derivative computation for each line in the x-axis to extract the contours of the Bi contact and MoS₂ ML (black lines) at the C.E. region. g, High-resolution dI/dV image with the same Bi contour at the C.E. determined in f, image acquired at sample bias V_s = +2.0 V, current I_t = 400 pA and source–drain voltage V_DS = 0.0 V. The white and red dashed lines in f and g represent the position of the STS line scans, as detailed in Supplementary Note 3. h, HR-XTEM image of Bi/MoS₂ interface (top) and the corresponding EDX element mapping (bottom). a.u., arbitrary units. Scale bars, 50 nm (e); 5 nm (f,g); 20 nm (h, top and bottom).

Large-range XSTM scanning was used in the experiment to locate the ML-MoS from the substrate to the top surface of the sample. Once the ML-MoS₂ was found, the direction of scanning measurement was switched to investigate along the direction parallel to the MoS₂ film until the Bi-MoS₂ C.E. was crossed over. For details of locating and identifying the MoS₂ layer and C.E., refer to Supplementary Notes 3 and 4. Then, we spatially scan through the MoS₂ to the C.E. and the channel after magnifying the scanning region to the MoS₂ under the Bi contact metal. Leveraging the inherent high resolution of STM, we can conduct the scanning tunnelling spectroscopy (STS) measurement at a specific distance from Bi to the bottom Si and distinctly identify the STS curves of MoS₂ with high spatial resolution (Fig. 3a). The STS data for Si show the bandgap measured at approximately 1.1 eV, consistent with existing studies²². For MoS₂, the observed bandgap was approximately 2.3 eV (ref. ²³). Bi shows a non-zero slope at zero voltage, indicating its metallic properties, whereas the SiO₂ between Si and MoS₂ shows a wide bandgap character, which is consistent with its dielectric role.

a, The STS evolution from Bi (green) to MoS₂ (yellow) to SiO₂ (brown) with 0.4 nm resolution at V_DS = 0.0 V with 0.4 nm resolution. We select the MoS₂ curve close to the oxide at each point for further STS analysis. b, Comparison of tunnelling spectra for MoS₂ under Bi_Drain at different distances (C.E., A, B to H correspond to 0–6.4 nm at a 0.8 nm interval) away from the C.E. with varying V_DS (0 V and 0.5 V). The dI/dV curves are plotted in logarithmic scale. The dotted lines indicate the position of the conduction band edge (E_C). See Supplementary Notes 9 and 13 for the counterpart figures to a and b for the device with HfO₂ as the dielectric layer. For the definition of the x-axis of STS data, \(E-{{E}_{\text{F}}}^{{\text{MoS}}_{2}}\), refer to Supplementary Note 14. c,d, Comparison of conduction band edges E_C under Bi source (c) and drain contacts (d) for MoS₂ devices with SiO₂ as gate dielectric under varying V_DS. The zero position of the x-axis corresponds to the C.E. e,f, Gate-voltage dependence of the conduction band edge E_C in the Bi/MoS₂/SiO₂ device at fixed V_DS = −0.5 V, measured near the source (e) and drain contacts (f). The measurements were performed at three different gate voltages (V_G = 0 V, 0.5 V and 2.0 V). For details of uncertainty calculation, refer to Supplementary Note 7. a.u., arbitrary units.

To systematically probe the carrier transport behaviour, we performed operando STS line scans to extract dI/dV curves of MoS₂ from the region under contact to the channel with two different gate dielectrics (20 nm HfO₂ and 100 nm SiO₂) under varying V_G and V_DS applied in situ. For performance comparison of devices with HfO₂ and SiO₂ as dielectric layers, refer to Supplementary Note 5. For details of optimizing spatial resolution and sampling strategy for the operando measurement, refer to Supplementary Note 3. The device with 100 nm SiO₂ enables comprehensive investigation of both V_DS and V_G while minimizing gate leakage. The measured conduction band (CB) edge energy evolves with the location as shown in Fig. 3b. To understand the detailed evolution of band structure, we first focus on analysing the energy-band shifts along the CB edge at the drain area using the device with a 100 nm SiO₂ dielectric layer at V_G = 0 V. The spatially resolved dI/dV spectra were collected at 0.8 nm intervals from the C.E. to 6.4 nm into the under-contact region. At V_DS = 0 V, the MoS₂ CB edge maintains a consistent value of (0.82 ± 0.02) eV across all positions, as indicated by the yellow dotted line in Fig. 3b. On applying V_DS = 0.5 V, we observe systematic shifts in all spectral curves, prompting a detailed analysis of the CB edge positions under different bias conditions, as presented in Fig. 3c,d. Note that the CB edge is extracted with the assumption that a linear region is observed on either side of the onset in the STS curve, as detailed in previous publications²⁴ and Supplementary Note 6. The error bars of CB values and difference are calculated by including the uncertainties from each CB measurement and using error propagation²⁵ to ensure a proper representation of the combined uncertainty (for details, see Supplementary Note 7). The position-dependent CB edge values measured on devices with both dielectric configurations reveal several key features. For the SiO₂-based device, at V_DS = 0 V, the CB maintains a uniform energy level throughout the measured region. On applying V_DS = −0.5 V, we observe that the CB edge of MoS₂ exhibits a position-dependent shift under the drain contact. This shift extends into the channel region, where the CB edge difference between two measured points (about 3 nm from the drain and about 3 nm from the source) is (0.45 ± 0.11) eV, primarily reflecting the channel voltage drop, given that contact resistance accounts for less than 1% of the total resistance (Fig. 1).

Meanwhile, there are two points worth noting: (1) On applying V_DS = −0.5 V, the MoS₂ CB edge are saturated and stabilized at a distance of 6 nm or more from the C.E. point as denoted by the universal energy shift \(\Delta {E}^{{\text{V}}_{\text{DS}}}\) in Fig. 3d. (2) The CB edge near the C.E. point (that is, 0–6 nm) exhibits an additional shift ∆E^edge, as shown in Fig. 3c,d, resulting in a more pronounced total energy shift ∆E_C. It is well acknowledged that the voltage drop across a device should be correlated to the resistance between two ends²⁶. However, this large shift ∆E^edge cannot be explained by the voltage drop because the contact resistance (R_c) is only 70 Ω, constituting less than 1% of the total resistance.

When measuring n-type semiconductors such as MoS₂ with STM, we focus on the CB rather than the valence band (VB) because the tip-sample system can be approximated to a metal-oxide semiconductor (MOS) structure. The measured CB edge position is influenced by two key factors. First, applying a positive bias to the sample leads to carrier depletion and a larger band bending at the surface, requiring a higher tunnelling bias to reach the CB onset. Conversely, when a negative bias is applied, carrier accumulation at the surface enhances the electric field screening, reducing the band bending²⁷. This difference in band bending causes the measured CB edge to deviate more from the actual value compared with the VB edge. Second, the onset of the tunnelling current (the measured band edge position) varies significantly depending on the local carrier concentration^28,29. Simulations of this so-called tip-induced band bending (TIBB) effect in Extended Data Fig. 3b indicate that changes in carrier concentration have a more pronounced effect on the CB than on the VB. In regions with fewer carriers, a higher voltage must be applied to detect efficient tunnelling current because of lower electric field screening efficiency. However, as the carrier concentration increases, the effect of TIBB weakens, resulting in measured CB and VB edge positions being closer to the real energy-band structure. For details of the band bending and band alignment evolution, refer to Supplementary Note 8.

Therefore, the observation of ∆E^edge is proposed to be attributed to the increase in carrier concentration at the C.E. edge because of the injection of carriers from the contact, causing the energy shift of the CB edge at the C.E. point from the weakening of the TIBB effect. This attribution is further strengthened by systematically ruling out alternative causes, such as defects, dopants or instrumental artefacts, as detailed in Supplementary Note 9. Notably, in the source region (Fig. 3c), the additional voltage drop ∆E^edge is noted at the points less than 6 nm from the source C.E. on applying an external voltage (V_DS = −0.5 V), whereas regions beyond 6 nm exhibit a consistent value, closely matching the CB value of MoS₂ at V_DS = 0 V. This consistency is attributed to the source serving as the ground for V_DS, where no additional voltage drop is expected. To confirm the reproducibility of our measurement model, we also conducted the STS measurement under different V_DS, as shown in Fig. 3c,d, and all of them show similar band bending behaviour at the C.E. To further understand the gate-voltage influence on carrier injection characteristics, we conducted measurements with fixed V_DS = −0.5 V while varying V_G using the SiO₂ device, as shown in Fig. 3e,f. These measurements show that both source and drain regions exhibit systematic changes in band bending magnitude and spatial extent with increasing gate voltage, which is consistent with our TLM measurement and previous literature^7,30. For details of V_G value selection for in situ XSTM measurement, refer to Supplementary Notes 10–12.

Following the definition of transfer length in TLM model³¹ as described by the length for which the voltage drops to 1/e in exponential decay functions fitting, we quantitatively analysed the fitting curve of the CB points and the corresponding transfer length (L_T) in various operating conditions in Fig. 3c–f and presented in Fig. 4a,b. Figure 4a shows the exponential fitting line of MoS₂ under drain and source contact regions after applying V_DS while V_G = 0 V. With the exponential decay fitting and defining 1/e as transfer length, it is appropriate to define the measured 2.0 nm as the transfer length for the SiO₂ device when V_DS = −0.5 V, and extend to 2.9 nm when V_G = 2 V is applied.

a, Exponential decay fitting of the additional band edge shift (∆E^edge) near the C.E. for Bi/MoS₂/SiO₂ devices under different V_DS conditions. The carrier concentration scale corresponds to the TIBB simulation results in Extended Data Fig. 3. The intrinsic carrier concentration n₀ for MoS₂/SiO₂ is 10¹¹cm⁻². b, Exponential decay fitting of the additional band edge shift (∆E^edge) near the C.E. for the Bi/MoS₂/SiO₂ device under different V_G conditions. Gate-voltage dependence of band edge decay profiles in Bi/MoS₂/SiO₂ device at fixed V_DS = −0.5 V shows a systematic increase in transfer length (L_T) with increasing V_G. The inset shows the definition of transfer length as the 1/e decay distance. For details of the fitting, refer to Supplementary Note 16. c, Schematic of MoS₂ band alignment and current injection path near the C.E. under bias operation. The blue curve is the band alignment considering the potential drop of the TLM model. \({\Delta E}^{{V}_{{\rm{D}}{\rm{S}}}}\) is the energy difference between the source and drain due to the applied source–drain voltage V_DS. The black dashed line is the quasi-Fermi level of MoS₂. L_T denotes the transfer length, which is measurable at the sub-nanometre scale in XSTM measurements. d, Comparison of the transfer length between MoS₂ and different metal contacts obtained through various methods. Direct, direct measurement from this work; Scaling, contact length scaling experiments; TLM, transfer length method extraction; Sim., theoretical simulations. The dashed lines indicate IRDS requirements for 1 nm and 3 nm technology nodes.

Next, we need to know how much of the change in carrier concentration causes the band shift at the C.E. Depending on the onset of the CB with different positions, we performed simulations based on the TIBB model³² (Extended Data Fig. 3) to extract how the carrier concentration changes with different distances from the C.E. points. For MoS₂ with lower carrier concentration, the onset of tunnelling current is higher because of the significant TIBB effect. By contrast, MoS₂ with higher carrier concentration has the measured position of the CB edge closer to the real value because of the weakening of the TIBB effect and the significant screening effect (Extended Data Fig. 3b). The change of the STS curves due to the change of carrier concentration is also shown in Extended Data Fig. 3c. Thus, the apparent additional shift of the CB edge, ∆E^edge, causing the CB edge to be closer to the Fermi level of the MoS₂ at the grounded source (\({{E}_{\text{F}}}^{{\text{MoS}}_{2}}\)), is due to carrier injection at the C.E. Note that, the CB of MoS₂ in the channel, after applying an external voltage, is elevated above the linear interpolation between the CB of source and drain C.E.s, which is due to the difference of TIBB effect on MoS₂ in the channel and under Bi contact, as shown in Extended Data Fig. 4. This difference (Δ₁ ≠ Δ₂) originates primarily from the altered electronic properties of MoS₂ underneath the Bi contact, such as electron affinity, work function and local dielectric environment^33,34,35, which collectively influence the local carrier distribution and thus the magnitude of band bending.

Furthermore, by comparing the ∆E_C values in the simulation results with our experimental results, we can infer that the carrier injecting through the MoS₂ at the C.E. is about two orders of magnitude higher than that of the MoS₂ > 2 nm from the C.E. at V_DS = −0.5 V as shown in Fig. 4a. The exponential decay fitting for the CB under contact in Fig. 3f is shown in Fig. 4b. We found that the transfer length is longer when gate bias increasing, which might be due to the current crowding effect that the longer distance is needed for more carrier to pass through. It is consistent with the results shown in Fig. 4a that the transfer length^36,37 would be longer when increasing the V_DS, which drives more carrier from drain to source. The schematic band diagram of MoS₂ device under operating is shown in Fig. 4c. This band diagram shows the intrinsic band alignment considering the potential drop of TLM model in V_DS applying situation and the transfer length (L_T) indicated in the figure is measurable at sub-nanometre scale in XSTM measurements. The observed exponential decay of the CB edge shift directly correlates with the spatial distribution of injected carriers, providing unprecedented insight into the carrier injection process at the metal–2D semiconductor interface. It is to be noted that the carrier transfer length in our XSTM measurement (2.0–2.9 nm) is lower than the previous result of MoS₂ FET with Bi contact in Fig. 1d, which is 9.25 nm, determined based on TLM model without using 1/e decay function at room temperature.

The application of TLM to estimate L_T, assuming R_sh = R_sk (where R_sh is the channel sheet resistance and R_sk is the sheet resistance under metal), could lead to differences if the metal contact alters the conductivity of the underlying channel material (MoS₂ in this case). In our experimental results, L_T is 9.25 nm, R_c is 70 Ω μm and channel resistance R_T is 66.8 kΩ μm at a channel length of 0.8 μm. Using these values in the conventional TLM equations, R_sh is calculated as 81.6 kΩ. However, in real situations R_sk shows a significant deviation from R_sh owing to contact doping (details in Supplementary Note 19), fabrication-induced damage and metal-induced gap states (MIGS)^17,18. By inserting the measured transfer length of 2.0 nm into the modified TLM equation¹⁷, R_sk is determined to be 380 kΩ, which is much larger than the original R_sh (81.6 kΩ). According to a modified TLM model for 2D devices¹⁷, when R_sk/R_sh < 1, the estimated transfer length exceeds that determined by conventional TLM, suggesting that if the contact metal enhances the conductivity of the underlying 2D material, the actual transfer length could be longer than that estimated using conventional TLM (R_sk = R_sh). This analysis highlights the importance and necessity of direct measurements in response to the trend of shrinking dimensions of forward-looking semiconductor devices.

To further confirm the validity of the methodology, we also investigated the transfer length of a Bi-contacted MoS₂ device with HfO₂ as dielectric, as shown in Extended Data Fig. 5 and a p-type WSe₂ device with Pd/Sb alloy contacts (6 nm of Sb followed by 20 nm of Pd) using XSTM. As the p-type contact resistance is still yet to be improved, spatially resolved the STS measurements were taken at a larger interval (40 nm). Analogous to n-type contact, the p-C.E. (Extended Data Fig. 6a) showed a significant VB shift towards the Fermi level on applying V_DS (Extended Data Fig. 6b,c). This observation is consistent with TIBB model simulations (Extended Data Fig. 6d,e), which show that the E_VB of WSe₂ is closer to the Fermi level when the carrier concentration is increased, whereas the E_C remains relatively unchanged. In p-type semiconductors such as WSe₂, the focus is on the VB rather than the CB because of the effects of TIBB. The difference between the measured and actual values of the VB is larger than that of the CB, and this difference is reduced by changes in carrier concentration. Consequently, the VB shift is more sensitive to variations in carrier concentration compared with the CB, making it a more suitable parameter for analysis in p-type semiconductors. The transfer length of WSe₂ with Pd/Sb alloy contacts was determined as approximately 211 nm (Extended Data Fig. 6c).

In conclusion, we use operando cross-sectional STM/STS to directly probe the carrier transfer length at metal/2D semiconductor interfaces with sub-nanometre spatial resolution. Figure 4d compiles our measured L_T on MoS₂ and those estimated based on direct contact scaling, simulation or TLM extraction. Our measurements show an ultrashort transfer length of about 2–3 nm for optimized Bi-MoS₂ contacts, satisfying the projected contact scaling requirements for the 1 nm technology node¹. These results provide direct experimental evidence that contact scaling in 2D transistors can extend well into the deep nanoscale regime, consistent with recent industry projections⁵. However, p-type contact is yet to be largely improved^17,38,39 (Extended Data Table 2).

Beyond 2D systems, we further validate the generality of our methodology through additional operando cross-sectional STM measurements on silicon-on-insulator (SOI) devices (Supplementary Note 20). In these conventional semiconductor structures, we successfully extract a transfer length of about 55 nm, in good agreement with values estimated using TLM. This consistency confirms that the proposed technique is not limited to 2D materials but is broadly applicable to established semiconductor platforms. Taken together, these results establish operando XSTM as a universal metrology for directly resolving carrier injection physics across a wide range of device architectures, spanning 2D materials, heterostructures and Si technologies. This ability provides an experimental foundation for understanding contact scaling limits and will play an important part in guiding the design of future ultra-scaled electronic devices.